View PI6C487016FBE_1295927.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PI6C487016
Low Skew, 1-to-16 LVCMOS / LVTTL Clock Driver
Product Features
* 16 LVCMOS/LVTTL outputs (4 banks of 4 outputs) * Selectable differential or single-ended clock inputs * CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * CLK0 supports the following input types: LVCMOS, LVTTL * Maximum output frequency: 250MHz * Independent bank control for /1 or /2 operation * Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V operations * Output skew: 170ps (max) * Bank skew: 50ps (max) * Part-to-part skew: 800ps (max) * 3.3V core, 3.3V, 2.5V, or 1.8V output operating supply * -40 to +85C ambient operating temperature * Available packages: -Pb-free & green 48-pin LQFP(FB)
Product Description
The PI6C487016 is a low skew. 1:16 LVCMOS/LVTTL Clock Driver. The device has 4 banks of 4 outputs and each bank can be independently selected for /1 or /2 frequency operation. Each bank also has its own power supply pins so that the banks can operate at the following different voltage levels: 3.3V, 2.5V, and 1.8V. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The divide select inputs, SELA:SELD, control the output frequency of each bank with either /1 or /2 frequency operation. The bank enable inputs, ENA:END, support enabling and disabling each bank of outputs individually. The outputs synchronized when enabling or disabling the clock outputs. The master reset input nMR/OE, resets the /1//2 flip flops and also controls the active and high impedance states of all outputs. The PI6C487016 is characterized to operate with the core at 3.3V and the output banks at 3.3V, 2.5V or 1.8V.
Block Diagram
Pin Description
QA3 VDDOA QA2 GND QA1 VDDOA QA0 GND CLK_SEL nCLK1 CLK1 VDD
nMR/OE CLK0 CLK1 nCLK1 CLK_SEL SELA SELB SELC SELD
1
1 0 0 1
/1 /2
1 0 1 0
D LE
4
QA0:QA3
D LE
4
QB0:QB3
D LE
4
QC0:QC3
D LE
0
4
QD0:QD3
ENA ENB ENC END
VDD CLK0 SELA SELB SELC SELD ENA ENB ENC END nMR/OE GND
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
GND QC2 VDDOC QC3 GND QD0 VDDOD QD1 GND QD2 VDDOD QD3
GND QB0 VDDOB QB1 GND QB2 VDDOB QB3 GND QC0 VDDOC QC1
1
PS8741D
07/29/05
PI6C487016 Low Skew, 1-to-16 LVCMOS/LVTTL Clock Driver
Pin Descriptions
Number 1, 48 2 3, 4, 5, 6 7, 8, 9, 10 11 12, 16, 20, 24, 28, 32, 36, 40, 44 13, 15, 17, 19 14, 18 21, 23, 25, 27 22, 26 29, 31, 33, 35 30, 34 37, 39, 41, 43 38, 42 45 46 47 Name VDD CLK0 SELA : SELD ENA : END nMR/OE GND QD0 : QD3 VDDOD QC0 : QC3 VDDOC QB0 : QB3 VDDOB QA0 : QA3 VDDOA CLK_SEL nCLK1 CLK1 Power Input Input Input Input Power Output Power Output Power Output Power Output Power Input Input input Pulldown Pullup Pulldown Pulldown Pullup Pullup Pullup Type Core supply pins (3.3V) LVCMOS / LVTTL clock input Controls frequency division for outputs. LVCMOS / LVTTL interface levels. QAx:QDx Output enable for QAx : QDx Outputs. Active HIGH. If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Master reset. When LOW, resets the /1//2 flip flops and sets the outputs to high impedance. LVCMOS / LVTTL interface levels. Supply Ground Bank D Outputs, LVCMOS / LVTTL interface levels. Voltage supply for QD0 : QD3 Bank C outputs, LVCMOS / LVTTL interface levels. Voltage supply for QC0 : QC3 Bank B outputs, LVCMOS / LVTTL interface levels. Voltage supply for QB0 : QB3 Bank A outputs, LVCMOS / LVTTL interface levels. Voltage supply for QA0 : QA3 Clock select input, when HIGH, selecs CLK1, nCLK1 inputs. When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. inverting differential clock input Non-inverting differential clock input Description
Notes: 1. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values.
Function Table
Inputs nMR/OE 0 1 1 1 ENx X 1 1 0 SELx X 0 1 X Bank X Hi Z Active Active Low Outputs Qx Frequency N/A FIN/2 FIN N/A
2
PS8741D
07/29/05
PI6C487016 Low Skew, 1-to-16 LVCMOS/LVTTL Clock Driver
Absolute Maxium Ratings
Supply Voltage, VDD ...................... 4.6V Inputs, VI...................................................... -0.5V to VDD +0.5V Outputs, V0.................................................. -0.5V to VDDO +0.5V Package Thermal Impedance, OJA ..... 47.9 C/W (0lfpm) Storage Temperature, TSTG................... -65C to +150C
Notes: 1. Stresses byond those listed under Absolute Maximun Ratings may caouse permanent damage to the device. These ratings are stress specifcations only. Functional operation of products at these conditions or any conditions beyond those listed in the DC Characteristics or AC characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Pin Characteristics
Symbol CIN RPULLUP CPD ROUT Parameter Input Capacitance Input Pullup Resistor Power Dissaipation Capacitance (per output) Output Impedance VDD, VDDOX = 3.465V VDD = 3.465, VDDOX = 2.625V VDD = 3.465, VDDOX = 1.895V 5 7 Test Condition Min. Typ. 4 51 51 18 20 30 12 pf Max. Units pF k
RPULLDOWN Input Pulldown Resistor
Power Supply DC Characteristics, (VDD = 3.3V 5%, TA = -40 to +85C)
Symbol VDD VDDOX IDD IDDOX Parameter Core Supply Voltage Output Supply Voltage Core Supply Current Output Supply Current(1) Min. 3.135 3.135 2.375 1.71 Typ. 3.3 3.3 2.5 1.8 Max. 3.465 3.465 2.625 1.89 100 15 mA V Units
Note: 1. Measured with all outputs disabled (ENx=0, nMR=1)
3
PS8741D
07/29/05
PI6C487016 Low Skew, 1-to-16 LVCMOS/LVTTL Clock Driver
LVCMOS/LVTTL DC Characteristics, (VDD = 3.3V 5%, TA = -40 to +85C)
Symbol VIH Parameter Input High Voltage SELx, ENX, nMR/OE, CLK_SEL CLK0 Input Low Voltage SELx, ENx, nMR/OE, CLK_SEL CLK0 ENx, SELx, Input High Current nMR/OE CLK0, CLK_SEL Input Low Current ENx, SELx, nMR/OE CLK0, CLK_SEL Output High Voltage(1) VDD = VIN = 3..465V -150 -5 2.6 1.8 VDD - 0.45 0.5 0.5 0.45 -5 5 A V Test Conditions Min. 2 2 -0.3 -0.3 Typ. Max. VDD + 0.3 VDD + 0.3 0.8 1.3 5 150 A V Units
VIL
IIH
IIL
VDD = 3.465, VIN = 0V VDDOX = 3.3 5%
VOH
VDDOX = 2.5 5% VDDOX = 1.8 5% IOH = -2mA VDDOX = 3.3 5% VDDOX = 2.5 5% VDDOX = 1.8 5% IOH = -2mA
VOL IOZL IOZH
Output Low Voltage(1) Output Tristate Current Low Output Tristate Curretn High
Notes: 1. Outputs terminate with 50 to VDDOX/2. See Parameter Measurement information, Output Load Test Circut
Differential DC Characteristics, (VDD = 3.3V 5%, TA = -40 to +85C)
Symbol IIH IIL VPP VCMR Parameter Input High Current Input Low Current nCLK1 CLK1 nCLK1 CLK1 voltage(1,2) Test Conditions VIN = VDD = 3.465V VIN = VDD = 3.465V VIN = 0V, VDD = 3.465V VIN = 0V, VDD = 3.465V -150 -5 0.15 GND + 0.5 1.3 VDD -0.85 V Min. Typ. Max. 5 150 A Units
Peak-to-peak Input Voltage Common mode input
Notes: 1. For single ended application, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V. 2. Common mode voltage is definded as VIH.
4
PS8741D
07/29/05
PI6C487016 Low Skew, 1-to-16 LVCMOS/LVTTL Clock Driver
AC Characteristics, (VDD = 3.3V 5%, VDDOX = 1.8V 5% to 3.3V 5%, TA = -40 to +85C)(7)
Symbol fMAX Parameter Output Frequency CLK0(1) CLK1, TpLH Propagation Delay, Low to High CLK1, CLK1, tsk(b) tsk(o) tsk(pp) tR/tF odc tEN tDIS Bank skew(3) skew(4) skew(5) 20% to 80% 200 40 Output nCLK1(2) nCLK1(2) nCLK1(2) CLK0(1) CLK0(1) VDDOX = 3.3V VDDOX = 2.5V VDDOX = 1.8V Measured on the rising edge Measured on the rising edge 2.3 2.5 2.3 2.5 2.4 2.6 3.4 3.4 3.5 3.5 3.9 3.9 Test Conditions Min. Typ. Max. 250 3.9 3.9 4.0 4.0 4.7 4.7 50 170 800 700 60 10 10 % ns ps ns Units MHz
Part-to-Part
Output Rise/Fall Time(5) Output duty cycle Output enable Output time(6) Disable Time(6)
Notes: 1. Measured from the VDD/2 of the input to VDDOX/2 of the output 2. Measured from the differential input crossing point to VDDOX/2 of the output 3. Defined as a skew within a bankwith equal load conditions 4. Defined as a skew between outputs at the same supply voltage, same frequency, and with equal load conditions. Measured at VDDOX/2 5. Defined as a skew between outputs on a different devices operation at the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. 6. These parameters are guaranteed by characterizatoin. Not tested in prodution. 7. All parameters are measured at 250MHz with SEL [A:D] = 1 unless noted otherwise.
5
PS8741D
07/29/05
PI6C487016 Low Skew, 1-to-16 LVCMOS/LVTTL Clock Driver
Parameter Measurement Information
1.65V5% 2.05V5% VDD, VDDOx 1.25V5%
SCOPE
VDD
Qx
SCOPE
VDDOx
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5% -1.25V5%
3.3V Core/3.3V Output Load AC Test Circuit
3.3V Core/2.5V Output Load AC Circuit
2.40.9V +0.9V5%
VDD
V DD VDDOx
SCOPE
Qx
nCLK1
LVCMOS
V
CLK1
PP
Cross Points
V
CMR
GND
GND = -0.9V5%
3.3V Core/1.8V Output Load AC Test Circuit
Differential Input Level
6
PS8741D
07/29/05
PI6C487016 Low Skew, 1-to-16 LVCMOS/LVTTL Clock Driver
Application Information Wiring the differenctial input to accept single ended levels
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 adn R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R1/R2 = 0.609.
VDD Single Ended Clock Input
R1 1K CLK1
nCLK1 C1 0.1 R2 1K
Figure 1: Single-ended Signal Driving Differential Input
7
PS8741D
07/29/05
PI6C487016 Low Skew, 1-to-16 LVCMOS/LVTTL Clock Driver
Package Mechanical: 48-pin LQFP (FB)
9.00 BSC
7.00 BSC
0.09~0.20
GAUGE PLANE
0.25 mm
7.00 BSC
1.45 1.35
1.60 MAX
9.00 BSC
0 7
0.45 0.75
1.00 REF
Seating Plane
0.17 0.27 0.50 BSC
0.05 0.15
0.10 C
Ordering Information
Ordering Code PI6C487016FBE Package Code FB Package Type Pb-free & Green, 48-pin LQFP
Notes: 1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/ 2. Number of Transistors = TBD
Pericom Semiconductor Corporation * 1-800-435-2336 * http://www.pericom.com
8
PS8741D 07/29/05

▲Up To Search▲

Price & Availability of PI6C487016FBE

	To Download PI6C487016FBE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .